1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to an architecture for a cache memory that employs a hybrid arrangement of cache tags.
2. Background
Prior computer systems commonly include one or more cache memories. A typical cache memory is a fast access memory that stores data reflecting selected locations in a corresponding main memory of the computer system. Such a cache memory is usually comprised of static random access memorys (SRAM). Typically, the data stored in such a cache memory is organized into data sets which are commonly referred to as cache lines or data lines.
Such cache memories usually include storage areas for a set of tags that correspond to each data line. Such tags typically include address tags that identify an area of the main memory that maps to the corresponding data line. In addition, such cache tags usually provide status information for the corresponding data line.
One type of cache memory is known as a write-back cache memory. Such a cache memory typically includes tag bits that indicate the update status of the data lines stored in the cache in relation to the corresponding data line in the main memory. Such status tag bits are commonly referred to as "dirty" tags. Typically, a dirty tag indicates whether the corresponding cache line contains updated or "dirty" information not reflected in the corresponding location in the main memory.
Such a write-back cache memory typically conserves the bandwidth for accesses to the corresponding main memory by preventing some possibly unneeded writes of data to the main memory when it is present in the cache. However, such a write-back cache requires that at least one dirty tag bit be allocated to each cache line entry, in order to manage data coherency between the cache and main memory. In addition, the time required to update a dirty tag bit during a write transaction is a limiting factor in the overall speed of write cycles to memory in such systems.
One prior type of write-back cache memory includes a standard SRAM that stores the cache memory tags. Typically, such a tag SRAM stores the address tags as well as clean/dirty and other status tags. Such a cache memory typically includes a cache controller circuit with internal comparators. Such a cache controller circuit typically reads the external tag SRAM during a memory write cycle and then determines whether the write cycle "hits" or "misses" a data line in data store portion of the cache memory. The cache controller circuit usually determines an updated value for the appropriate dirty tag if a write hit is detected. Such a write-back cache offers the advantage of relatively low cost due to the availability in volume of external standard tag SRAM. Unfortunately, such cache memories usually provide relatively low performance during write cycles due to the speed limitations imposed by updates of the tag SRAM during write hits.
Other prior write-back cache memories employ custom tag SRAMs that include internal registers. Such custom tag SRAMs typically latch the address of write transactions to enable the proper updating of the dirty tag bits during high bandwidth write transactions. Unfortunately, such custom tag SRAMs are typically much more expensive than standard SRAM based tags and increases the overall cost of such a computer system.
Still other prior write-back cache memories employ custom cache controllers that include integrated tag SRAMs. Such custom integrated tag SRAMs enable fast update of internal dirty tag bits during write transactions. Unfortunately, such an integration of SRAM with a cache controller typically increases the overall cost of the cache memory. In addition, prior cache controller design technologies such as application specific integrated circuits are not well suited for the implementation of custom tag SRAMs.